MegaProcessor

Update of "Programming Model"
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Overview

Artifact ID: e7a50e235fa844933d945ee65e9707f3deb04530
Page Name:Programming Model
Date: 2015-07-30 16:11:24
Original User: jos
Parent: fea2c8054c960fa8ad696a63ecd4eb04f0967eab
Content

General Purpose Registers

The Mega-processor has four general purpose 16 bit registers: R0, R1, R2, R3.

There are 12 1-byte instructions to move data around from any general purpose register to any other.

R0 can also exchange data with the Stack Pointer (SP) -- instructions MOVE R0,SP and move SP,R0 --,
and with the program counter -- instructions JMP (R0) and JSR (R0) --

R2 and R3 can also serve as index registers with optional automatic postincrement.

Program Counter

There is a 16 bit program counter, PC.

Stack Pointer

There is a 16 bit register dedicated as the stack pointer SP.

The PUSH instruction performs a predecrement save of a register (R0..R3, PS)
The POP instruction performs a postincrement restore of a register.
R0..R3 are saved/restored as 16 bit values, PS is saved/restored as 8 bits.
There are also 2 specific MOVE instructions to move data from SP to R0, or vice-versa.

Processor Status Register

There is a processor status register, PS. Whilst PS is internally a 16 bit register only 8 bit are visible to the user.
The other hidden 8 bits are used during complex operations such as multiplication etc. and do not convey any information from one instruction to the next.

The user accessible status bits are:

0 I Enable interrupts. Set/cleared by user.
Also cleared on servicing an interrupt/exception.
1 N Set/cleared when result is negative/positive
2 Z Set/cleared when result is zero/non-zero
3 V Set/cleared when there was/was not an overflow
4 X Set/cleared when there was a carry
(not cleared on non-arithmetic operations so can be used for extended arithmetic)
5 C Set/cleared when there was a carry
6 D Controls division mode
7 U User bit.
May be used for conditional branches,
the BUS and BUC instructions are provided for this.
Does not otherwise affect, and is not affected by processor operation
but must be set/cleared explicitly by user.