MegaProcessor

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Overview
Comment:Added logic to calculate the length of an instruction.
Downloads: Tarball | ZIP archive | SQL archive
Timelines: family | ancestors | descendants | both | trunk
Files: files | file ages | folders
SHA1:07910336296441df53e25572a3d661539eff1f6c
User & Date: jos 2015-08-11 23:19:30
Context
2015-08-13
12:07
DRYed up most io.write(string.format(...)) things, and some other cleanup. check-in: a639fc9186 user: jos tags: trunk
2015-08-11
23:19
Added logic to calculate the length of an instruction. check-in: 0791033629 user: jos tags: trunk
21:50
Added opcode for NOP_x (0xc5) check-in: 2acd1fa545 user: jos tags: trunk
Changes
Hide Diffs Unified Diffs Ignore Whitespace Patch

Changes to asm.lua.

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        io.write( string.format("%04d  ", LineNr) );        
        ProcessLine( Chomp(l) );
        LineNr = LineNr + 1;
    end
end

function Fields( line )
    if( line == "" or line:match("^%s*//") ) then return 0; end;
    local retVal = 0;
    local n, n1, label, instr, dst, src;
    n = 1;
    label,n1 = line:match("^(%S+)()");  -- Start of string, (one+ non-space), (empty capture)
    if( label ) then n=n1; retVal = retVal + 1; end
    instr,n1 = line:match("%s+([^%s,;]+)%s+()",n); -- one+ space, (one+ non-space), one+ space, (empty capture)
    if( instr ) then n=n1; retVal = retVal + 1; end
................................................................................
    return retVal, label, instr, dst, src;
end

function ProcessLine( l )
    local asm_instr;
    local n,f1,f2,f3,f4 = Fields(l);
    local b1, b2, b3, formBytes;



    if( n == 0 ) then print(l); return; end

    asm_instr = Directive[ string.lower(f2 or f3) ];
    if( asm_instr ) then print( asm_instr() ); return; end
    
    asm_instr = CPU_instr[ string.upper(f2 or f3) ];
   
    if( asm_instr ) then 


        b1, b2, b3 = asm_instr[2](f2,f3,f4);
    end
    n, formBytes = fmtBytes(b1, b2, b3);

    io.write( formBytes ); print( l );

end


-- Main line
--
if( not arg[1] ) then







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        io.write( string.format("%04d  ", LineNr) );        
        ProcessLine( Chomp(l) );
        LineNr = LineNr + 1;
    end
end

function Fields( line )
    if( line == "" or line:match("^%s*[;//]") ) then return 0; end;
    local retVal = 0;
    local n, n1, label, instr, dst, src;
    n = 1;
    label,n1 = line:match("^(%S+)()");  -- Start of string, (one+ non-space), (empty capture)
    if( label ) then n=n1; retVal = retVal + 1; end
    instr,n1 = line:match("%s+([^%s,;]+)%s+()",n); -- one+ space, (one+ non-space), one+ space, (empty capture)
    if( instr ) then n=n1; retVal = retVal + 1; end
................................................................................
    return retVal, label, instr, dst, src;
end

function ProcessLine( l )
    local asm_instr;
    local n,f1,f2,f3,f4 = Fields(l);
    local b1, b2, b3, formBytes;
    local insLen;


    if( n == 0 ) then print(l); return; end

    asm_instr = Directive[ string.lower(f2 or f3) ];
    if( asm_instr ) then print( asm_instr() ); return; end
    
    asm_instr = CPU_instr[ string.upper(f2 or f3) ];
   
    if( asm_instr ) then
        insLen = asm_instr[1];
        if( type(insLen)== 'function' ) then insLen = insLen(f2,f3,f4) end;
        b1, b2, b3 = asm_instr[2](f2,f3,f4);
    end
    n, formBytes = fmtBytes(b1, b2, b3);

    io.write( string.format("%d:%s",insLen,formBytes) ); print( l );

end


-- Main line
--
if( not arg[1] ) then

Changes to opcodes.lua.

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  return 0xcd ;
end

function do_XOR(f1, f2, f3)
    return( 0x20 + isReg2(f2,f3) );
end










































--
-- Table for CPU instructions in mnemonic format
--   element 1 = instruction length in bytes: 0 means operand-dependent length.
--   emement 2
--
CPU_instr = {
  ['ABS'] = { 1, do_ABS },
  ['ADD'] = { 1, do_ADD },
  ['ADDI'] = { 1, do_ADDI },
  ['ADDQ'] = { 1, do_ADDQ },
  ['ADDX'] = { 1, do_ADDX },
  ['AND'] = { 0, do_AND },  -- 2 if op1 is PS, 1 otherwise.
  ['ANDI'] = { 2, do_ANDI }, -- alias for AND PS,#VV ;
  ['ASL'] = { 2, do_ASL },
  ['ASL.WT'] = { 2, do_ASL_WT },
  ['ASR'] = { 2, do_ASR },
  ['ASR.WT'] = { 2, do_ASR_WT },
  ['BCC'] = { 2, do_BCC },
  ['BCHG'] = { 2, do_BCHG },
................................................................................
  ['DEC'] = { 1, do_DEC },
  ['DIVS'] = { 1, do_DIVS },
  ['DIVU'] = { 1, do_DIVU },
  ['DIV.S'] = { 1, do_DIVS },  -- Alias for DIVS
  ['DIV.U'] = { 1, do_DIVU },  -- Alias for DIVU
  ['INC'] = { 1, do_INC },
  ['INV'] = { 1, do_INV },
  ['JMP'] = { 0, do_JMP },  -- 1 if op1 = (R0), otherwise 3.
  ['JSR'] = { 0, do_JSR },  -- 1 if op1 = (R0), otherwise 3.
  ['LD.B'] = { 0, do_LD_B },
  ['LD.W'] = { 0, do_LD_W },
  ['LSL'] = { 2, do_LSL },
  ['LSL.WT'] = { 2, do_LSL_WT },
  ['LSR'] = { 2, do_LSR },
  ['LSR.WT'] = { 2, do_LSR_WT },
  ['MOVE'] = { 1, do_MOVE },
  ['MULS'] = { 1, do_MULS },
  ['MULU'] = { 1, do_MULU },
  ['NEG'] = { 1, do_NEG },
  ['NEGX'] = { 1, do_NEGX },
  ['OR'] = { 0, do_OR },  -- 2 if op1 is PS, 1 otherwise.
  ['ORI'] = { 2, do_ORI }, -- alias for OR PS,#VV ;
  ['NOP'] = { 1, do_NOP },
  ['NOP_X'] = { 1, do_NOP_X },  -- Unused instruction.
  ['POP'] = { 1, do_POP },
  ['PUSH'] = { 1, do_PUSH },
  ['RET'] = { 1, do_RET },
  ['RETI'] = { 1, do_RETI },
................................................................................
  ['ROR'] = { 2, do_ROR },
  ['ROR.WT'] = { 2, do_ROR_WT },
  ['ROXL'] = { 2, do_ROXL },
  ['ROXL.WT'] = { 2, do_ROXL_WT },
  ['ROXR'] = { 2, do_ROXR },
  ['ROXR.WT'] = { 2, do_ROXR_WT },
  ['SQRT'] = { 1, do_SQRT },
  ['ST.B'] = { 0, do_ST_B },
  ['ST.W'] = { 0, do_ST_W },
  ['SUB'] = { 1, do_SUB },
  ['SUBX'] = { 1, do_SUBX },
  ['SXT'] = { 1, do_SXT },
  ['TEST'] = { 1, do_TEST },
  ['TRAP'] = { 1, do_TRAP },
  ['XOR'] = { 1, do_XOR },
};







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  return 0xcd ;
end

function do_XOR(f1, f2, f3)
    return( 0x20 + isReg2(f2,f3) );
end

----------------------------------------------------------------------------------------
function len_A_O(f1,f2,f3)
    if( f2:upper() == 'PS')
        then return 2
        else return 1
    end
end

function len_JMP(f1,f2,f3)
    if( f2:sub(1,1) == '(' ) then return 1 else return 3 end;
end

function len_LD_B(f1,f2,f3)
    -- print(f1,f2,f3);
    if( f3:sub(1,1) == "#" ) then return 2 end;  -- LD.B Rx, #0xWW (4 cases)
    if( f3:match("^%( *[sS][pP]") ) then return 2 end; -- LD.B Rx,(SP,0xWW) (4 cases)
    if( f3:match("^%( *[rR]") ) then return 1 end; -- LD.B Ra,(Rb[++]) (8 cases)
    return 3; -- LD.B 0xWWWW (4 cases)
end

function len_LD_W(f1,f2,f3)
    -- print(f1,f2,f3);
    if( f3:sub(1,1) == "#" ) then return 3 end;  -- LD.W Rx, #0xWWWW (4 cases)
    if( f3:match("^%( *[sS][pP]") ) then return 2 end; -- LD.W Rx,(SP,0xWW) (4 cases)
    if( f3:match("^%( *[rR]") ) then return 1 end; -- LD.W Ra,(Rb[++]) (8 cases)
    return 3; -- LD.W 0xWWWW (4 cases)
end

function len_ST_B(f1,f2,f3)
    if( f2:match("^%( *[sS][pP]") ) then return 2 end; -- ST.B (SP,0xWW),Rx (4 cases)
    if( f2:match("^%( *[rR]") ) then return 1 end; -- ST.B (Rb[++]),Ra (8 cases, 4 w/o and 4 with '++' )
    return 3; -- ST.B Rx 0xWWWW (4 cases)
end

function len_ST_W(f1,f2,f3)
    if( f2:match("^%( *[sS][pP]") ) then return 2 end; -- ST.W (SP,0xWW),Rx (4 cases)
    if( f2:match("^%( *[rR]") ) then return 1 end; -- ST.W (Rb[++]),Ra (8 cases, 4 w/o and 4 with '++' )
    return 3; -- ST.W Rx 0xWWWW (4 cases)
end

----------------------------------------------------------------------------------------
--
-- Table for CPU instructions in mnemonic format
--   element 1 = instruction length in bytes: 0 means operand-dependent length.
--   emement 2
--
CPU_instr = {
  ['ABS'] = { 1, do_ABS },
  ['ADD'] = { 1, do_ADD },
  ['ADDI'] = { 1, do_ADDI },
  ['ADDQ'] = { 1, do_ADDQ },
  ['ADDX'] = { 1, do_ADDX },
  ['AND'] = { len_A_O, do_AND },  -- 2 if op1 is PS, 1 otherwise.
  ['ANDI'] = { 2, do_ANDI }, -- alias for AND PS,#VV ;
  ['ASL'] = { 2, do_ASL },
  ['ASL.WT'] = { 2, do_ASL_WT },
  ['ASR'] = { 2, do_ASR },
  ['ASR.WT'] = { 2, do_ASR_WT },
  ['BCC'] = { 2, do_BCC },
  ['BCHG'] = { 2, do_BCHG },
................................................................................
  ['DEC'] = { 1, do_DEC },
  ['DIVS'] = { 1, do_DIVS },
  ['DIVU'] = { 1, do_DIVU },
  ['DIV.S'] = { 1, do_DIVS },  -- Alias for DIVS
  ['DIV.U'] = { 1, do_DIVU },  -- Alias for DIVU
  ['INC'] = { 1, do_INC },
  ['INV'] = { 1, do_INV },
  ['JMP'] = { len_JMP, do_JMP },  -- 1 if op1 = (R0), otherwise 3.
  ['JSR'] = { len_JMP, do_JSR },  -- 1 if op1 = (R0), otherwise 3.
  ['LD.B'] = { len_LD_B, do_LD_B },
  ['LD.W'] = { len_LD_W, do_LD_W },
  ['LSL'] = { 2, do_LSL },
  ['LSL.WT'] = { 2, do_LSL_WT },
  ['LSR'] = { 2, do_LSR },
  ['LSR.WT'] = { 2, do_LSR_WT },
  ['MOVE'] = { 1, do_MOVE },
  ['MULS'] = { 1, do_MULS },
  ['MULU'] = { 1, do_MULU },
  ['NEG'] = { 1, do_NEG },
  ['NEGX'] = { 1, do_NEGX },
  ['OR'] = { len_A_O, do_OR },  -- 2 if op1 is PS, 1 otherwise.
  ['ORI'] = { 2, do_ORI }, -- alias for OR PS,#VV ;
  ['NOP'] = { 1, do_NOP },
  ['NOP_X'] = { 1, do_NOP_X },  -- Unused instruction.
  ['POP'] = { 1, do_POP },
  ['PUSH'] = { 1, do_PUSH },
  ['RET'] = { 1, do_RET },
  ['RETI'] = { 1, do_RETI },
................................................................................
  ['ROR'] = { 2, do_ROR },
  ['ROR.WT'] = { 2, do_ROR_WT },
  ['ROXL'] = { 2, do_ROXL },
  ['ROXL.WT'] = { 2, do_ROXL_WT },
  ['ROXR'] = { 2, do_ROXR },
  ['ROXR.WT'] = { 2, do_ROXR_WT },
  ['SQRT'] = { 1, do_SQRT },
  ['ST.B'] = { len_ST_B, do_ST_B },
  ['ST.W'] = { len_ST_W, do_ST_W },
  ['SUB'] = { 1, do_SUB },
  ['SUBX'] = { 1, do_SUBX },
  ['SXT'] = { 1, do_SXT },
  ['TEST'] = { 1, do_TEST },
  ['TRAP'] = { 1, do_TRAP },
  ['XOR'] = { 1, do_XOR },
};